1. Field of the Invention
The present invention relates to an overcurrent relay. More specifically, the present invention relates to an overcurrent relay in which a reset time is shortened.
2. Description of the Prior Art
An overcurrent relay is one kind of a protective relay and is used for protection of a power line, for example.
FIG. 1 is an outline view showing one example of a power line. A power line 2 is coupled through a circuit breaker 3 to a power source 1. A current transformer 4 is operatively coupled to the power line 2 on the side of the power source 1 with respect to the breaker 3. An overcurrent relay 5 is coupled to the current transformer 4 and a control circuit 6 is coupled to the output of the overcurrent relay 5. The output of the control circuit 6 is coupled to the circuit breaker 3. In the case where a failure occurs in the power line 2, for example, in the case where a failure occurs at a failure point F.sub.S or F.sub.L, a large ac input current I flows from the current transformer 4 to the overcurrent relay 5. The overcurrent relay 5 is responsive thereto to provide an operation signal S.sub.1 and the control circuit 6 is responsive to the operation signal S.sub.1 to trip the circuit breaker 3. Thus, the power line 2 is protected.
FIG. 2 is a block diagram showing a conventional overcurrent relay. An input terminal IN of an input transformer 7 is coupled to the current transformer 4 shown in FIG. 1. The output of the input transformer 7 is coupled to an input of a rectifying circuit 8 and the output of the rectifying circuit 8 is coupled to the input of a level detecting circuit 9. The output of the level detecting circuit 9 is coupled to an output terminal OUT and the output terminal OUT is coupled to the input of the control circuit 6 shown in FIG. 1. The input transformer 7 serves to convert the ac input current I from the current transformer 4 into an ac signal voltage V.sub.1. The rectifying circuit 8 rectifies the ac signal voltage V.sub.1 to provide a dc signal voltage E. The level detecting circuit 9 provides an operation signal S.sub.1 when the dc signal voltage E exceeds a predetermined value.
FIG. 3 is a schematic diagram of one example of the rectifying circuit 8. The FIG. 3 embodiment comprises a full-wave rectifying and smoothing circuit employing a well-known operational amplifier. An operation thereof will be briefly described. The ac signal voltage V.sub.1 is half-wave rectified by a circuit mainly comprising an operational amplifier 81, and a half-wave rectified voltage of the ac signal voltage V.sub.1 of inverted polarity is obtained at the junction 83. An operation is made of the ac signal voltage V.sub.1 and the above described half-wave rectified voltage and a smoothing operation is also performed by means of a circuit mainly comprising an operational amplifier 82, whereby a full-wave rectified direct current signal voltage E is provided.
FIG. 4 is a block diagram showing one example of the level detecting circuit 9. A stretching timer circuit 92 is coupled to a voltage comparator 91. The plus input terminal of the voltage comparator 91 is connected to receive the dc signal voltage E and the minus input terminal of the voltage comparator 91 is connected to receive a predetermined set voltage E.sub.R. The voltage comparator 91 serves to compare the dc signal voltage E and the predetermined set voltage E.sub.R, thereby to provide the dc signal voltage E.sub.1 when E&gt;E.sub.R. The stretching timer circuit 92 serves to stretch the dc signal voltage E.sub.1 by a predetermined time period T.sub.1, thereby to provide the operation signal S.sub.1. The purpose of providing the stretching timer circuit 92 will be described. In the case where the set voltage E.sub.R is slightly larger than the dc signal voltage E, the direct current signal voltage E.sub.1 is obtained in a form which is interrupted and conducted for each half cycle of the ac input current I. Therefore, the stretching timer circuit 92 is provided to make continuous the intermittent dc signal voltage E.sub.1 to provide a continuous operation signal S.sub.1. Accordingly, a predetermined time period T.sub.1 for stretching is selected to be approximately a half-cycle of the line source voltage, i.e. approximately 10 msec in the case when the frequency of the line source is of 50 Hz, for example.
FIG. 5 is a schematic diagram showing one example of the stretching timer circuit 92. An integrating capacitor 923 is coupled to the output of a switching transistor 921. The capacitor 923 is coupled through a Zener diode 924 to a switching transistor 922. Operation of the circuit will now be briefly described with reference to FIG. 6. FIG. 6 is a graph showing waveforms of the signals at various portions of the FIG. 5 diagram. Assuming that the waveform of the dc signal voltage E.sub.1 is as shown in the figure, when the dc signal voltage E.sub.1 attains the low level, the transistor 921 is turned off and the voltage E.sub.2 of the capacitor 923 starts increasing. When the voltage E.sub.2 reaches the Zener voltage V.sub.Z of the Zener diode 924, the transistor 922 is turned on, so that the operation signal S.sub.1, which has thus far assumed the high level, assumes the low level. Accordingly, it follows that the operation signal S.sub.1 is stretched by the time period T.sub.5 as compared with the dc signal voltage E.sub.1. Since the value of the time period T.sub.5 can be arbitrarily changed as a function of the capacitance of the capacitor 923, the same is selected to be equal to the above described time period T.sub.1.
Operation of the conventional overcurrent relay shown in FIG. 2 will now be described with reference to FIGS. 7 and 8. FIG. 7 is a graph showing waveforms of the signals at various portions in the FIG. 2 overcurrent relay in the case where a failure occurs in the power line 2. FIG. 8 is a graph showing waveforms of the signals at various portions in the FIG. 2 overcurrent relay in the case where a failure occurs at the point very close to the point where the overcurrent relay is provided in the power line 2.
Now mainly referring to FIG. 7, assuming that a failure occurred at a time t.sub.1 at the failure point F.sub.L of the power line 2, a large amount of the ac input current I flows from the current transformer 4 into the input transformer 7 and the ac signal voltage V.sub.1 is obtained from the input transformer 7, where an ordinary load current before occurrence of the failure is neglected for simplicity of description. The dc signal voltage E is obtained from the rectifying circuit 8 and, at the time point t.sub.2 when the dc signal voltage E exceeds the set voltage E.sub.R, the operation signal S.sub.1 is obtained from the level detecting circuit 9. The control circuit 6 is responsive to the operation signal S.sub.1 to trip the circuit breaker 3, whereby the circuit breaker 3 is tripped at the time t.sub.3. As a result, the ac signal voltage V.sub.1 becomes zero at the time t.sub.3 ; however, the ac signal voltage E gradually attenuates by virtue of the capacitor included in the rectifying circuit 8 and becomes smaller than the set voltage E.sub.R at the time t.sub.4. However, the operation signal S.sub.1 assumes the low level at a point in time delayed by the time period T.sub.1 with respect to the time t.sub.4, the delay provided by means of the stretching timer circuit 92 included in the level detecting circuit 9, whereby the relay is reset. Accordingly, the reset time period of the relay in such case is T.sub.R1.
Now mainly referring to FIG. 8, assuming a case where a failure occurs at the time t.sub.1 at the failure point F.sub.s very close to the point where the relay is installed in the power line 2, a failure current flowing to the power line 2 becomes extremely large. In such case, if an overcurrent factor of the current transformer 4 is small, the ac input current I becomes a much distorted waveform due to magnetic saturation of the core of the current transformer 4, whereby the ac signal voltage V.sub.1 also becomes an extremely distorted waveform. Now by an overcurrent factor of the current transformer 4 is meant a ratio of the maximum current in which the primary current and the secondary current are kept in a linear relation to the rated current, which is usually denoted by (n). In such case a, even if the circuit breaker 3 is tripped at the time t.sub.3 and a failure current flowing through the power line 2 becomes zero, the secondary current of the current transformer 4, i.e. the alternating current input current I, does not immediately become zero and assumes a form of an attenuating dc component, which gradually becomes zero. Accordingly, an attenuating dc component V.sub.1 ' is involved in the ac signal voltage V.sub.1 and the attenuating dc component E' is involved in the dc signal voltage E. As a result, the dc signal voltage E becomes smaller than the the set voltage E.sub.R at the time t.sub.5 which is much later than the time t.sub.3, whereby the reset time period of the relay becomes T.sub.R2, which is extremely longer than the above described reset time period T.sub.R1. This is not convenient to an overcurrent relay. This will be described in detail in the following.
Usually a main protective relay and a back-up relay are employed in a protective relaying system of a power line. A main protective relay usually comprises a relay capable of high speed operation, while the back-up relay is implemented by a relay capable of an assured operation, such as an overcurrent relay. In the case where a failure occurs in a power line, both relays operate, although the circuit breaker is tripped by the main protective relay. Both relays are reset due to the tripping of the circuit breaker. However, if and when the reset time period of the overcurrent relay is too long, the circuit breaker is deemed as not having been tripped due to some trouble of the circuit breaker in the control circuit in spite of the fact that the circuit breaker has been tripped, whereby there is a concern for the possibility that another operation is performed in which the circuit breaker is forcedly tripped by means of a separate route or a further operation is performed in which the other circuit breaker of the same power line is forcedly tripped. In particular, when the other circuit breaker is forcedly tripped, the section where a failure has not occurred is brought in the state of power failure, with the result of a considerable amount of damage. Therefore, it has been desired to provide an overcurrent relay in which a reset time period is not prolonged, even if an attenuated dc component is included in the ac input current of the relay, as in a case where a failure occurs in a close vicinity of the point where a relay is installed.